COMPREHENSIVE FUNCTIONAL VERIFICATION: THE COMPLETE INDUSTRY CYCLE

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.

As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.

A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.

* Comprehensive overview of the complete verification cycle
* Combines industry experience with a strong emphasis on functional verification fundamentals
* Includes industry examples and real-world case studies

Part I: Introduction to Verification

Chapter 1: Verification in the Chip Design Process
1.1 Introduction to Functional Verification
1.2 The Verification Challenge
1.3 Mission and Goals of Verification
1.4 Cost of Verification
1.5 Areas of Verification beyond the scope of this book
1.6 The Verification Cycle: A Structured Process
1.7 Summary
1.8 Exercises

Chapter 2: Verification Flow
2.1 Verification Hierarchy
2.2 Strategy of Verification
2.3 Summary
2.4 Exercises

Chapter 3: Fundamentals of Simulation Based Verification
3.1 Basic Verification Environment: A Test Bench
3.2 Observation Points: Black-box, White-box and Grey-box verification
3.3 Assertion Based Verification - An overview
3.4 Test benches and Testing Strategies
3.5 Summary
3.6 Exercises

Chapter 4: The Verification Plan
4.1 The Functional Specification
4.2 The Evolution of the Verification Plan
4.3 Contents of the Verification Plan
4.4 Verification example: Calc1
4.5 Summary
4.6 Exercises

Part II: Simulation Based Verification

Chapter 5: HDLs and Simulation Engines

5.1 Hardware Description Languages
5.2 Simulation Engines - Introduction
5.3 Event-Driven Simulation
5.4 Improving Simulation Throughput
5.5 Cycle-Based Simulation
5.6 Waveform Viewers
5.7 Summary
5.8 Exercises

Chapter 6: Creating Environments
6.1 Testbench Writing Tools
6.2 Verification Coverage
6.3 Summary
6.4 Exercises

Chapter 7: Strategies for Simulation based Stimulus Generation
7.1 Calc2 Overview
7.2 Strategies for Stimulus Generation
7.3 Summary
7.4 Exercises

Chapter 8: Strategies for Results Checking in Simulation Based Verification
8.1 Types of Result Checking
8.2 Debug
8.3 Summary
8.4 Exercises

Chapter 9: Pervasive Function Verification
9.1 System Reset and Bring-up
9.2 Error and Degraded Mode Handling
9.3 Verifying Hardware Debug Assists
9.4 Low Power Mode Verification
9.5 Summary
9.6 Exercises

Chapter 10: Re-Use Strategies and System Simulation
10.1: Re-Use Strategies
10.2: System Simulation
10.3: Beyond General Purpose Logic Simulation
10.4: Summary
10.5: Exercises

Part III: Formal Verification

Chapter 11 Introduction to Formal Verification
11.1 Foundations
11.2 Formal Boolean Equivalence Checking
11.3 Functional Formal Verification - Property Checking
11.4 Summary
11.5 Exercises

Chapter 12 Using Formal Verification
12.1 Property Specification Using an HDL Library
12.2 The Property Specification Language PSL
12.3 Property Checking Using Formal Verification
12.4 Summary
12.5 Exercises

Part IV: Comprehensive Verification

Chapter 13: Completing the Verification Cycle
13.1 Regression
13.2 Problem Tracking
13.3 Tape-Out Readiness
13.4 Escape Analysis
13.5 Summary
13.6 Exercises

Chapter 14: Advanced Verification Techniques
14.1 Save verification cycles - bootstrapping the verification process
14.2 High-Level modeling - concepts
14.3 Coverage-Directed Generation
14.4 Summary
14.5 Exercises

Part V: Case Studies

Chapter 15: Case Studies
15.1 The Line Delete Escape
15.2 Branch History Table
15.3 Network Processor
15.4 Summary
Glossary
References