購物比價找書網找車網
FindBook  
 有 2 項符合

DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS

的圖書
DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS

作者:MING-BO LIN(NTUST) 
出版社:全華
出版日期:2008-09-25
圖書介紹 - 資料來源:三民網路書店   評分:
圖書名稱:DIGITAL SYSTEM DESIGNS AND PRACTICES: USING VERILOG HDL AND FPGAS
  • 圖書簡介

    System-on-a-chip (SoC) has become an essential technique to lower product costs and maximize power efficiency, particularly as the mobility and size requirements of electronics continues to grow. It has therefore become increasingly important for electrical engineers to develop a strong understanding of the key stages of hardware description language (HDL) design flow based on cell-based libraries or field-programmable gate array (FPGA) devices. Honed and revised through years of classroom use, Lin focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL.
    Explains how to perform synthesis and verification to achieve optimized synthesis results and compiler times
    Offers complete coverage of Verilog syntax
    Illustrates the entire design and verification flow using an FPGA case study
    Presents real-world design examples such as LED and LCD displays, GPIO, UART, timers, and CPUs
    Emphasizes design/implementation tradeoff options, with coverage of ASICs and FPGAs
    Provides an introduction to design for testability
    Gives readers deeper understanding by using problems and review questions in each chapter
    Comes with downloadable Verilog HDL source code for most examples in the text
    Includes presentation slides of all book figures for student reference
    Digital System Designs and Practices Using Verilog HDL and FPGAs is an ideal textbook for either fundamental or advanced digital design courses beyond the digital logic design level. Design engineers who want to become more proficient users of Verilog HDL as well as design FPGAs with greater speed and accuracy will find this book indispensable.

  • 作者簡介

    Ming-Bo Lin is a Professor of Electronic Engineering at National Taiwan University of Science and Technology, and has served as adjunct Professor at National Taiwan University. He has been teaching Computer Engineering and Microelectronics for over twenty years. Lin's research interests include VLSI system design, mixed-signal integrated circuit designs, parallel architectures and algorithms, and embedded computer systems. He has published over forty journal and conference papers in these areas. In addition, Lin has directed the designs of over thirty ASICs and has consulted in industry extensively in the fields of ASIC, SoC, and embedded system designs. During the past twenty years, he has translated two books and authored over ten books in Traditional Chinese.
    Lin holds a B.Sc.degree in Electronic Engineering from the National Taiwan Institute of Technology, an M.Sc.degree in Electrical Engineering from National Taiwan University, and a Ph.D. in Electrical Engineering from the University of Maryland, College Park.

  • 目次

    PREFACE.
    CHAPTER 1 INTRODUCTION.
    1.1 Introduction.
    1.2 Introduction to Verilog.
    1.3 Module Modeling Styles.
    1.4 Simulation.
    CHAPTER 2 STRUCTURAL MODELING.
    2.1 Gate-Level Modeling.
    2.2 Gate Delays.
    2.3 Hazards.
    2.4 Switch-Level Modeling.
    CHAPTER 3 DATAFLOW MODELING.
    3.1 Dataflow Modeling.
    3.2 Operands.
    3.3 Operators.
    CHAPTER 4 BEHAVIORAL MODELING.
    4.1 Procedural Constructs.
    4.2 Procedural Assignments.
    4.3 Timing Control.
    4.4 Selection Statements.
    4.5 Iterative (Loop) Statements.
    CHAPTER 5 TASKS, FUNCTIONS AND UDPS.
    5.1 Tasks.
    5.2 Functions.
    5.3 System Tasks and Functions.
    5.4 User-Defined Primitives.
    CHAPTER 6 HIERARCHICAL STRUCTURAL MODELING.
    6.1 Module.
    6.2 generate Statement.
    6.3 Configurations.
    CHAPTER 7 ADVANCED MODELING TECHNIQUES.
    7.1 Sequential and Parallel Blocks.
    7.2 Procedural Continuous Assignments.
    7.3 Delay Models and Timing Checks.
    7.4 Compiler Directives.
    CHAPTER 8 COMBINATIONAL LOGIC MODULES.
    8.1 Decoders.
    8.2 Encoders.
    8.3 Multiplexers.
    8.4 Demultiplexers.
    8.5 Magnitude Comparators.
    8.6 A Case Study: Seven-Segment LED Display.
    CHAPTER 9 SEQUENTIAL LOGIC MODULES.
    9.1 Flip-Flops.
    9.2 Memory Elements.
    9.3 Shift Registers.
    9.4 Counters.
    9.5 Sequence Generators.
    9.6 Timing Generators.
    CHAPTER 10 DESIGN OPTIONS OF DIGITAL SYSTEMS.
    10.1 Design Options of Digital Systems.
    10.2 PLD Modeling.
    10.3 CPLD.
    10.4 FPGA.
    10.5 Practical Issues.
    11 SYSTEM DESIGN METHODOLOGY.
    11.1 Finite-State Machine.
    11.2 RTL Design.
    11.3 RTL Implementation Options.
    11.4 A Case Study: Liquid-Crystal Displays.
    CHAPTER 12 SYNTHESIS.
    12.1 Design Flow of ASICs and FPGA-Based Systems.
    12.2 Design Environment and Constraints.
    12.3 Logic Synthesis.
    12.4 Language Structure Synthesis.
    12.5 Coding Guidelines.
    CHAPTER 13 VERIFICATION.
    13.1 Functional Verification.
    13.2 Simulation.
    13.3 Test Bench Design.
    13.4 Dynamic Timing Analysis.
    13.5 Static Timing Analysis.
    13.6 Value Change Dump (VCD) Files.
    13.7 A Case Study: FPGA-Based Design and Verification Flow.
    CHAPTER 14 ARITHMETIC MODULES.
    14.1 Addition and Subtraction.
    14.2 Multiplication.
    14.3 Division.
    14.4 Arithmetic and Logic Unit.
    14.5 Digital-Signal Processing Modules.
    CHAPTER 15 DESIGN EXAMPLES.
    15.1 Bus.
    15.2 Data Transfer.
    15.3 General-Purpose Input and Output.
    15.4 Timers.
    15.5 Universal Asynchronous Receiver and Transmitter.
    15.6 A Simple CPU Design.
    16 DESIGN FOR TESTABILITY.
    16.1 Fault Models.
    16.2 Test Vector Generation.
    16.3 Testable Circuit Design.
    16.4 System-Level Testing.
    APPENDIX A VERILOG HDL SYNTAX.
    A.1 Keywords.
    A.2 Source Syntax.
    A.3 Declarations.
    A.4 Primitive Instances.
    A.5 Module and Generated Instantiation.
    A.6 UDP Declaration and Instantiation.
    A.7 Behavioral Statements.
    A.8 Specify Section.
    A.9 Expressions.
    A.10 General.
    INDEX.

贊助商廣告
 
金石堂 - 今日66折
存債致富:每月3000元,輕鬆投資債券抗通膨,穩穩賺,資產不縮水
作者:郭雅芸(辣媽Shania)
出版社:時報文化出版企業股份有限公司
出版日期:2024-03-26
66折: $ 251 
金石堂 - 今日66折
肉の料理科學【超圖解】:1000張分解圖!大廚不外傳的雞豬牛羊306個部位烹調密技,從選對肉到出好菜一本搞定!
作者:朝日新聞出版
出版社:台灣廣廈有聲圖書有限公司
出版日期:2020-10-08
66折: $ 317 
金石堂 - 今日66折
台股安穩因子投資法:每年花8小時,報酬近20%,天天睡得著的股票投資法
作者:葉怡成
出版社:財經傳訊
出版日期:2023-12-14
66折: $ 454 
 
金石堂 - 暢銷排行榜
隱性潛能:華頓商學院最具影響力教授,突破天賦極限的實證科學【附潛能提升秘訣卡】
作者:亞當.格蘭特
出版社:平安文化有限公司
出版日期:2024-07-29
$ 379 
Taaze 讀冊生活 - 暢銷排行榜
發酵大豆抗癌新希望
作者:呂鋒洲
出版社:元氣齋
出版日期:2002-07-01
$ 140 
Taaze 讀冊生活 - 暢銷排行榜
靈界運作:全面理解靈界生態,同步保護並健全自己的能量,讓身心再進化
作者:小湛
出版社:遠流出版事業股份有限公司
出版日期:2023-01-17
$ 292 
金石堂 - 暢銷排行榜
老夫老妻重返青春(8)完
作者:新挑限
出版社:台灣角川股份有限公司
出版日期:2025-04-17
$ 111 
 
Taaze 讀冊生活 - 新書排行榜
背著善宰跑:劇本集
作者:李施恩
出版社:時報文化出版企業股份有限公司
出版日期:2025-03-11
$ 1260 
Taaze 讀冊生活 - 新書排行榜
故事劇本診療室:無論新手老手都想知道的70個寫作解方
作者:東默農
出版社:原點出版
出版日期:2025-04-25
$ 385 
Taaze 讀冊生活 - 新書排行榜
自然資本經濟學:建立與自然共好的商業模式與創新解方
作者:希達斯.施里坎特
出版社:日出出版
出版日期:2025-02-26
$ 420 
金石堂 - 新書排行榜
小平安.上
$ 237 
 

©2025 FindBook.com.tw -  購物比價  找書網  找車網  服務條款  隱私權政策