Verilog HDL: Digital Design and Modeling

Cavanagh (Santa Clara University) introduces the language elements and expressions of the Verilog hardware description language (HDL) for simulating digital systems, and explains the dataflow, behavioral, and structural modeling constructs. Also appropriate for practicing computer engineers, the graduate textbook provides design examples complete with the design module, the test bench module, the outputs, and the waveforms. Annotation ©2007 Book News, Inc., Portland, OR (booknews.com)