Brunvand

　　Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.

1 Introduction
1.1 CAD Tool Flows
1.1.1 Custom VLSI and Cell Design Flow
1.1.2 Hierarchical Cell/Block ASIC Flow
1.2 What This Book Is and Isn’t
1.3 Bugs in the Tools?
1.4 Tool Setup and Execution Scripts
1.5 Typographical Conventions

2 Cadence DFII and ICFB
2.1 Cadence Design Framework
2.2 Starting Cadence
2.3 Summary

3 Composer Schematic Capture
3.1 Starting Cadence and Making a New Working Library
3.2 Creating a New Cell
3.2.1 Creating the Schematic View of a Full Adder
3.2.2 Creating the Symbol View of a Full Adder
3.2.3 Creating a Two-Bit Adder Using the FullAdder Bit
3.3 Schematics that Use Transistors
3.4 Printing Schematics
3.4.1 Modifying PostScript Plot Files
3.5 Variable, Pin, and Cell Naming Restrictions
3.6 Summary

4 Verilog Simulation
4.1 Verilog Simulation of Composer Schematics
4.1.1 Verilog-XL: Simulating a Schematic
4.1.2 NC Verilog: Simulating a Schematic
4.2 Behavioral Verilog Code in Composer
4.2.1 Generating a Behavioral View
4.2.2 Simulating a Behavioral View
4.3 Stand-Alone Verilog Simulation
4.3.1 Verilog-XL
4.3.2 NC Verilog
4.3.3 VCS
4.4 Timing in Verilog Simulations
4.4.1 Behavioral Versus Transistor Switch Simulation
4.4.2 Behavioral Gate Timing
4.4.3 Standard Delay Format (SDF) Timing
4.4.4 Transistor Timing
4.5 Summary

5 Virtuoso Layout Editor
5.1 An Inverter Schematic
5.1.1 Starting Cadence icfb
5.1.2 Making an Inverter Schematic
5.1.3 Making an Inverter Symbol
5.2 Layout for an Inverter
5.2.1 Creating a New layout View
5.2.2 Drawing an nmos Transistor
5.2.3 Drawing a pmos Transistor
5.2.4 Assembling the Inverter from the Transistor Layouts
5.2.5 Using Hierarchy in Layout
5.2.6 Virtuoso Command Overview
5.3 Printing Layouts
5.4 Design Rule Checking
5.4.1 DIVA Design Rule Checking
5.5 Generating an Extracted View
5.6 Layout Versus Schematic Checking (LVS)
5.6.1 Generating an analog-extracted View
5.7 Overall Cell Design Flow (So Far...)
5.8 Summary

6 Standard Cell Design Template
6.1 Standard Cell Geometry Specification
6.2 Standard Cell I/O Pin Placement
6.3 Standard Cell Transistor Sizing
6.4 Summary

7 Spectre Analog Simulator
7.1 Simulating a Schematic (Transient Simulation)
7.2 Simulation with the Spectre Analog Environment
7.3 Simulating with a Config View
7.4 Mixed Analog/Digital Simulation
7.4.1 Final Words about Mixed-Mode Simulation
7.5 DC Simulation
7.5.1 Parametric Simulation
7.6 Power Measurements
7.7 Summary

8 Cell Characterization
8.1 Liberty File Format
8.1.1 Combinational Cell Definition
8.1.2 Sequential Cell Definition
8.1.3 Tristate Cell Definition
8.2 Cell Characterization with ELC
8.2.1 Generating the ELC Netlist
8.2.2 Cell Naming and Encounter Library Characterizer
8.2.3 Best, Typical, and Worst Case Characterization
8.3 Cell Characterization with Spectre
8.4 Converting Liberty to Synopsys Database (db) Format
8.5 Summary

9 Verilog Synthesis
9.1 Synopsys Design Compiler Synthesis with dc shell
9.1.1 Basic Synthesis
9.1.2 Scripted Synthesis
9.1.3 Synopsys Design Vision GUI
9.1.4 DesignWare Building Blocks
9.2 Cadence RTL Compiler Synthesis
9.2.1 Scripted Synthesis
9.2.2 Cadence RTL Compiler GUI
9.3 Importing Structural Verilog into Cadence DFII
9.4 Post-Synthesis Verilog Simulation
9.5 Summary

10 Abstract Generation
10.1 Reading Your Library into Abstract
10.2 Finding Pins in Your Cells
10.3 The Extract Step10.4 The Abstract Step
10.5 LEF File Generation
10.6 Modifying the LEF File
10.7 Summary

11 SOC Encounter Place and Route
11.1 Encounter GUI
11.1.1 Reading In the Design
11.1.2 Floorplanning
11.1.3 Power Planning
11.1.4 Placing the Standard Cells
11.1.5 First Optimization Phase
11.1.6 Clock Tree Synthesis
11.1.7 Post-CTS Optimization
11.1.8 Final Routing
11.1.9 Post-Route Optimization
11.1.10 Adding Filler Cells
11.1.11 Checking the Result
11.1.12 Saving and Exporting the Placed and Routed Cell
11.1.13 Reading the Cell Back into Virtuoso
11.2 Design Import with Configuration Files
11.2.1 Floorplanning
11.3 SOC Encounter Scripting
11.4 Summary

12 Chip Assembly
12.1 Module Routing with ccar
12.1.1 Preparing a Placement with Virtuoso-XL
12.1.2 Invoking the ccar Router
12.2 Core to Pad Frame Routing with ccar
12.2.1 Copy the Pad Frame
12.2.2 Modify the Frame schematic View
12.2.3 Modify the Frame layout View
12.2.4 Routing the Core to Frame with ccar
12.2.5 Metal Density Issues
12.3 Final GDSII Generation
12.4 Summary

13 Design Example
13.1 Tiny MIPS
13.2 Tiny MIPS: Flat Tool Flow
13.2.1 Synthesis
13.2.2 Place and Route
13.2.3 Simulation
13.2.4 Final Assembly
13.3 Tiny MIPS: Hierarchical Tool Flow
13.3.1 Synthesis
13.3.2 Place and Route into a Macro Block
13.3.3 Preparing Custom Circuits for Hierarchy
13.3.4 Generating Abstract Views for Blocks
13.3.5 Place and Route with Macro Blocks
13.3.6 Simulation
13.3.7 Final Assembly
13.4 Summary

A Tool and Setup Scripts
A.1 Cadence Tool Installation
A.2 Cadence Setup Scripts
A.2.1 setup-cadence: Basic Cadence Setup
A.2.2 setup-ncsu: Cadence Setup with NCSU Extensions
A.3 Shell Scripts for Cadence Tools
A.3.1 syn-abstract: Start the Abstract Tool
A.3.2 cad-alf2lib: Convert the alf Notation from Encounter Library Characterizer to lib Notation
A.3.3 cad-elc: Start the Encounter Library Characterizer
A.3.4 cad-ncsu: Start the DFII (icfb) Environment
A.3.5 cad-soc: Start the SOC Encounter Place and Route Tool
A.3.6 sim-ncg: Startup Script for the NC Verilog Simulator, with GUI
A.3.7 sim-xlg: Startup Script for the Verilog-XL simulator, with GUI
A.3.8 sptr2elc: Perl Script for Converting Spectre Netlists to Encounter Library Characterizer Netlists
A.3.9 syn-rtlg: Start the RTL Compiler Synthesis Tool, with GUI
A.4 Synopsys Tool Installation
A.5 Synopsys Setup Scripts
A.5.1 setup-synopsys: Basic Synopsys Setup
A.6 Shell Scripts for Synopsys Tools
A.6.1 sim-vcs: Startup Script for the VCS Verilog Simulator
A.6.2 sim-simv: Startup Script for the simv Simulator Resulting from VCS Execution
A.6.3 syn-dc: Startup Script for Design Compiler Synthesis
A.6.4 syn-dv: Startup Script for Design Compiler using the Design Vision GUI
A.7 Summary

B Scripts to Drive the Tools
B.1 Tcl Script Basics
B.2 Cadence Tool Scripts
B.2.1 Encounter Library Characterizer Cell Characterization
B.2.2 Cell Characterization with Spectre
B.2.3 SOC Encounter Place and Route
B.2.4 RTL Compiler Synthesis
B.2.5 ccar Chip Assembly Tool
B.3 Synopsys Tool Scripts
B.3.1 Synopsys Design Compiler Script Files
B.4 Summary

C Technology and Cell Libraries
C.1 NCSU Cadence Design Kit CDK1.5 Installation
C.1.1 .cdsinit: Local Modifications
C.1.2 .cdsenv: Local Modifications
C.1.3 UofU TechLib ami06: Local Modifications
C.2 Example Standard Cells
C.2.1 Example Liberty File
C.2.2 LEF File Technology Header
C.2.3 LEF File MACRO Examples
C.3 Summary Bibliography Index