Fundamental Logic Design(基礎邏輯設計)

1　BackgroundKnowledgeandConcepts
1.1　AnIntroductiontoDigitalSystems
1.2　IntroductiontoLogicGates
1.2.1　PropertiesofLogicGatesbesidestheLogic
1.3　TheSpaceofOrderedn-tuplesofTwo-valuedVariables
1.4　NumberSystems(數系)andNumberRepresentations
1.5　InformationEncoding
1.5.1　Data
1.5.2　ControlSignals
1.6　ErrorDetectingandErrorCorrectionCodes
1.6.1　1-bitError-DetectingCodeusingParityCheck
1.6.2　TheHammingCodes(漢明碼)

2　SwitchingAlgebra
2.1　AxiomaticDefinitionofBooleanAlgebra
2.2　DefinitionoftheSwitchingAlgebra
2.3　DualityofLogic
2.4　IndirectMethodsofUnderstandingorProving TheoremsinBooleanAlgebra
2.4.1　UsingTruthTables(真值表)
2.4.2　UsingSetOperations(集合運算)
2.5　LogicFunctions
2.5.1　LogicFunctionsofOneVariableX
2.5.2　LogicFunctionsofTwoVariablesXandY
2.6　OtherBinaryLogicOperators
2.7　DefaultPrecedenceofOperationswithinanExpression
2.8　TheDeMorgan\’\’sTheorems
2.9　ExtensionoftheLogicOperatorstoOperateonMoreThanTwoVariables
2.10　FunctionsofThreeorMoreVariables
2.11　SimplificationofBooleanFunctions---AlgebraicMeth
2.12 SimplificationofBooleanFunctions---UsingK-maps
2.12.1　UsingK-mapsforFunctionswithDon\’\’t-CareConditio
2.13 ThePetrick\’\’sMethodandtheTabulationMethod
2.13.1　ThePetrick\’\’sMethod
2.13.2　SimplificationofBooleanFunctionsUsingtheTabulationMethod
2.14　DeMorgan\’\’sTheoremsrevisited

3　CombinationalLogicCircuits
3.1　LogicGatesandLogicFamilies
3.1.1　LogicGateSymbols
3.1.2　LogicFamilies
3.1.2.1　TTLNANDGates
3.1.2.2　CMOSLogicGatesandTransmissionGates
3.2　2-levelvs.Multi-levelCircuits
3.3　AllNANDCircuits
3.4　AnalysisandDesignofCombinationalCircuits
3.4.1　AnalysisofCombinationalCircuits
3.4.2　DesignofCombinationalCircuits
3.5　HazardsinCombinationalCircuits 3-29
3.6　CircuitsforDecisionMaking/Selection
3.6.1　Decoders
3.6.1.1　TheBasicn×2nDecoders
3.6.1.2　DecoderswithEnable
3.6.2　Multiplexers
3.7　CircuitsforMakingIdentifications
3.7.1　BasicEncoders
3.7.2　ThePriority4×2Encoder(加權式編碼器)
3.8　CircuitsthatEmulateBinaryArithmeticOperations
3.9　ProgrammableLogicDevices

4 IntroductiontoAsynchronousSequentialCircuits
4.1　AGeneralDescriptionofAsynchronousSequentialCircu
4.2　AnalysisofAsynchronousSequentialCircuits
4.3　Level-SensitiveGatedLatches
4.4　Master-SlaveFlip-flops
4.5　Edge-TriggeredFlip-flops
4.6　DesignofAsynchronousSequentialCircuits
4.7　AnAsynchronousCounter

5 IntroductiontoSynchronousSequentialCircuits
5.1　AGeneralDescriptionofSynchronousSequentialCircui
5.2　TimingConsiderationsforSynchronousSequentialCircu
5.3　AnalysisofSynchronousSequentialCircuits
5.4Immediate(Direct)InputsofEdge-TriggeredFlip-flops
5.5　AnOutlineoftheDesignProceduresforSynchronousSequentialCircuits
5.6　Registers
5.7　SynchronousCounters
5.8　SerialDataProcessing
5.9　BasicTimingorSequenceControlforRepetitiveActivi
5.10　ProceduresfortheDesignofSynchronousSequentialCi
5.11　TheASM(AlgorithmicStateMachine)Chart